50 GHz RSFQ pseudo-random number generator design

Simple RSFQ gates can be very robust, and operate up to high clock speeds in simulation. Larger RSFQ circuits are generally much more limited in clock speed. We believe that this is partly due to less than optimal choice of the timing inter-connections between gates. Timing design is especially problematic for circuits including data loops (feedback). We have developed a new technique for timing design of RSFQ data loops which may be called “balanced skew clock scheduling.” It involves equalizing the minimum clock period between every pair of gates. Mathematical analysis proves the optimality of this scheme and reveals the global timing constraints unique to RSFQ data loops. We used this technique for the design of a simple useful clocked RSFQ circuit, a four-bit pseudo-random number generator (PRNG). Constructed from our standard library cells for a 3.5 μm 1000 A/cm ² Nb-trilayer process, the PRNG worked up to 50 GHz in Jspice simulation