• DocumentCode
    1475561
  • Title

    Multilayer Global Routing With Via and Wire Capacity Considerations

  • Author

    Hsu, Chin-Hsiung ; Chen, Huang-Yu ; Chang, Yao-Wen

  • Author_Institution
    Grad. Inst. of Electron. Eng., Nat. Taiwan Univ. (NTU), Taipei, Taiwan
  • Volume
    29
  • Issue
    5
  • fYear
    2010
  • fDate
    5/1/2010 12:00:00 AM
  • Firstpage
    685
  • Lastpage
    696
  • Abstract
    Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing is presented. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage.
  • Keywords
    integrated circuit design; network routing; large-scale circuit designs; multilayer global routing; multiple metal layers; residual via capacity; routing congestion model; Circuit synthesis; Design for manufacture; Integrated circuit manufacture; Integrated circuit technology; Integrated circuit yield; Large-scale systems; Nonhomogeneous media; Routing; Semiconductor device manufacture; Wire; Congestion; global routing; layout; physical design;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2010.2043575
  • Filename
    5452098