Component development for a 16 Gb/s RSFQ-CMOS interface system

Author

Yoshikawa, Nobuyuki ; Abe, Takashi ; Kato, Yohsuke ; Hoshina, Hiroshi

Author_Institution

Fac. of Eng., Yokohama Nat. Univ., Japan

Volume

11

Issue

1

fYear

2001

fDate

3/1/2001 12:00:00 AM

Firstpage

735

Lastpage

738

Abstract

We have been developing an RSFQ-CMOS interface system. The system consists of three modules: a 1 to 32 bit DDST demultiplexer which converts a 16 Gb/s SFQ data input into a 32-channel 500 Mb/s output, asynchronous stacked-SQUID amplifiers which amplify an SFQ data input into a 5 mV voltage level output, and 77 K CMOS amplifiers which amplify a 5 mV voltage level input into a 5 V output at 500 MHz. We have implemented the asynchronous stacked-SQUID amplifier and the 77 K CMOS amplifier using the HYPRES 1 kA/cm² Nb process and the ROHM 0.6 μm CMOS process, respectively. It was demonstrated that the 24-stage asynchronous stacked-SQUID amplifier amplifies an SFQ data input into a 2.0 mV voltage level at 600 MHz. The 77 K CMOS amplifier was shown to amplify a 5 mV voltage level input into 5 V at 500 MHz from the simulation, and a 175 mV voltage input into 3.5 V at 90 MHz from the experiment

Keywords

CMOS integrated circuits; SQUIDs; cryogenic electronics; demultiplexing equipment; superconducting integrated circuits; 0.6 micron; 1 to 32 bit; 16 Gbit/s; 500 MHz; 600 MHz; 77 K; 90 MHz; CMOS amplifier; DDST demultiplexer; HYPRES process; Nb; ROHM process; RSFQ-CMOS interface circuit; SFQ data; asynchronous stacked SQUID amplifier; superconducting digital electronics; CMOS logic circuits; CMOS process; Clocks; Flip-flops; Josephson junctions; Radiofrequency amplifiers; SQUIDs; Semiconductor optical amplifiers; System testing; Voltage;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.919450

Filename

919450