Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze two design alternatives to improve cell hardening compatible with regular cell layouts providing an extensive analysis to illustrate the benefits of each technique. One of the proposed solutions is based on transistor width modulation that provides an immunity enhancement at the cost of a moderate cell-size increase. The other solution is based on multithreshold voltage selection showing a moderate immunity improvement at the cost of no impact on the cell area. The combination of both techniques is shown to be optimum when considering other design metrics like static noise margin, read/write stability, access time, and leakage. Results are demonstrated on 90- and 65-nm commercial technologies.