Abstract :
A pencil-and-paper method of designing multi-level logic circuits is presented. The approach is intuitive rather than systematic. It bears the same relation to the design of circuits with gates of limited fan-in (as is the case with most microcircuit families) as does the Karnaugh-map method to two-level circuits and gates with unlimited fan-in, NAND/NOR systems are considered, and a graphical procedure, based on Karnaughmaps, is followed.
