SINIS process development for integrated circuits with characteristic voltages exceeding 250 μV

At PTB, the fabrication process in Nb-Al/Al_xO_y /Al/Al_xO_y/Al-Nb SINIS multilayer technology has been improved to raise the characteristic voltage of SINIS two-tunnel Josephson junctions up to V_C=I_CR_n =245 μV. The process has been realized in LTS implementation. Various sets of the test wafers and wafers containing dc/SFQ and SFQ/dc converters, Josephson transmission lines, and T-flipflop circuits were fabricated and measured. The critical current densities of the junctions have been varied in the range from 70 A/cm² to 2.2 kA/cm² with corresponding characteristic voltages of V_C =55 μV and 245 μV at the temperature of 4.2 K. The junctions show nearly hysteresis-free behaviour (less than 15%), the intra-wafer parameter spread is smaller than ±10%. RSFQ circuits have been realized with operation margins of the bias currents larger than ±20%