Title :
An efficient VLSI architecture for real-time additive synthesis of musical signals
Author :
De Bernardinis, Fernando ; Roncella, Roberto ; Saletti, Roberto ; Terreni, Pierangelo ; Bertini, Graziano
Author_Institution :
Pisa Univ., Italy
fDate :
3/1/1999 12:00:00 AM
Abstract :
This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infinite-impulse-response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. A chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to 11 chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-/spl mu/m CMOS technology and has a core area of approximately 19 mm/sup 2/.
Keywords :
CMOS digital integrated circuits; IIR filters; VLSI; acoustic generators; electronic music; real-time systems; signal synthesis; systolic arrays; 0.5 micron; 44.1 kHz; 60 MHz; CMOS technology; VLSI architecture; bit-level systolic array; core area; independent output channels; musical signals; musical sound generation; real-time additive synthesis; real-time synthesis; sampling rate; second-order infinite-impulse-response filter; CMOS integrated circuits; CMOS technology; Clocks; Filters; Frequency; Hardware; Integrated circuit synthesis; Sampling methods; Systolic arrays; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
