Title :
Threshold logic network synthesis with specific threshold-gate sensitivities
fDate :
6/1/1972 12:00:00 AM
Abstract :
The sensitivity characteristics of threshold logic gates have been shown to be dependent upon the Chow parameter values of the gates. This information is here extended to enable threshold circuit synthesis to be undertaken using gates of chosen sensitivity, a requirement akin in Boolean synthesis to using Boolean gates with chosen fan-in limitations.
Keywords :
logic circuits; logic design; sensitivity; sensitivity analysis; threshold logic; Boolean synthesis; Chow parameter values; fan in limitations; sensitivity characteristics; threshold circuit synthesis; threshold logic gates;
Journal_Title :
Radio and Electronic Engineer
DOI :
10.1049/ree.1972.0047
