• DocumentCode
    1477624
  • Title

    Two high-bandwidth memory bus structures

  • Author

    Millar, Bruce ; Gillingham, Peter

  • Author_Institution
    MOSAID Technol. Inc., Kanata, Ont., Canada
  • Volume
    16
  • Issue
    1
  • fYear
    1999
  • Firstpage
    42
  • Lastpage
    52
  • Abstract
    The authors evaluate two next-generation memory bus architectures approximating SLDRAM and Direct Rambus. Quantifying sources of errors that degrade signal integrity, and considering power dissipation, they show that a fully loaded SLDRAM configuration has a greater timing margin than Direct Rambus
  • Keywords
    DRAM chips; SRAM chips; memory architecture; system buses; Direct Rambus; SLDRAM; errors; high-bandwidth memory bus structures; next-generation memory bus architectures; power dissipation; signal integrity; synchronous link DRAM; timing; Bandwidth; Distributed parameter circuits; Integrated circuit modeling; Intersymbol interference; Lead; Memory architecture; Packaging; Random access memory; Resistors; SDRAM;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.748804
  • Filename
    748804
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1477624