DocumentCode
1477647
Title
Estimating the economic benefits of DFT
Author
Butler, Kenneth M.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
Volume
16
Issue
1
fYear
1999
Firstpage
71
Lastpage
79
Abstract
Economic analyses based on cost alone are not sufficient for determining whether to include design for testability in complex or high-volume products. Cost avoidance and benefit terms should also be considered. The article proposes cost model components (as opposed to a complete cost model) that quantify cost avoidance and benefits terms for straightforward applications of scan design. For a large volume, complex IC such as the Texas Instruments TMS320C80, also known as the MVP, these components show how testability features have resulted in large revenue returns, both recurring and nonrecurring. Furthermore, there are other benefit and cost avoidance components that could be added beyond those discussed here. So the actual revenue increase may be larger than this analysis suggests. Note that all calculations and model parameter values given throughout the article are examples only and are not related to actual calculations witnessed in manufacturing
Keywords
Texas Instruments computers; cost-benefit analysis; design for testability; microprocessor chips; DFT; MVP; Texas Instruments TMS320C80; complex IC; cost avoidance; cost model components; cost/benefit analysis; design for testability; economic benefit analysis; high-volume products; model parameter values; revenue increase; scan design; testability features; Automatic test pattern generation; Automatic testing; Cost benefit analysis; Cost function; Design for testability; Differential equations; Flip-flops; Instruments; Maintenance engineering; Manufacturing automation;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.748807
Filename
748807
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