CMOS scaling into the nanometer regime

Author

Taur, Yuan ; Buchanan, Douglas A. ; Chen, Wei ; Frank, David J. ; Ismail, Khalid E. ; Lo, Shih-Hsein ; Sai-Halasz, George A. ; Viswanathan, Raman G. ; Wann, Hsing-Jen C. ; Wind, Shalom J. ; Wong, Hon-Sum

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

85

Issue

4

fYear

1997

fDate

4/1/1997 12:00:00 AM

Firstpage

486

Lastpage

504

Abstract

Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET´s, low-temperature CMOS, and double-gate MOSFET´s, which may lead to the outermost limits of silicon scaling

Keywords

CMOS integrated circuits; VLSI; integrated circuit interconnections; lithography; nanotechnology; silicon-on-insulator; CMOS scaling; MOSFETs; SOI; dopant number fluctuations; double-gate transistors; fundamental physical effects; gate oxide; high-field effects; interconnect delays; lithography; low-temperature CMOS; nanometer regime; power supply; short-channel effect; threshold voltage; CMOS logic circuits; CMOS technology; Delay; Lithography; Logic devices; MOSFET circuits; Power supplies; Silicon; Threshold voltage; Very large scale integration;

fLanguage

English

Journal_Title

Proceedings of the IEEE

Publisher

ieee

ISSN

0018-9219

Type

jour

DOI

10.1109/5.573737

Filename

573737