• DocumentCode
    1477985
  • Title

    Nanoelectronic architecture for Boolean logic

  • Author

    Roychowdhury, Vwani P. ; Janes, David B. ; Bandyopadhyay, Supriyo

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
  • Volume
    85
  • Issue
    4
  • fYear
    1997
  • fDate
    4/1/1997 12:00:00 AM
  • Firstpage
    574
  • Lastpage
    588
  • Abstract
    A nanoelectronic implementation of Boolean logic circuits is described where logic functionality is realized through charge interactions between metallic dots self-assembled on the surface of a double-barrier resonant tunneling diode (RTD) structure. The primitive computational cell in this architecture consists of a number of dots with nearest neighbor (resistive) interconnections. Specific logic functionality is provided by appropriate rectifying connections between cells. We show how basic logic gates, leading to combinational and sequential circuits, can be realized in this architecture. Additionally, architectural issues including directionality, fault tolerance, and power dissipation are discussed. Estimates based on the current-voltage characteristics of RTD´s and the capacitance and resistance values of the interdot connections indicate that static power dissipation as small as 0.1 nW/gate and switching delay as small as a few picoseconds can be expected. We also present a strategy for fabricating/synthesizing such systems using chemical self-organizing/self-assembly phenomena. The proposed synthesis procedure utilizes several chemical self-assembly techniques which have been demonstrated recently, including self-assembly of uniform arrays of close-packed metallic dots with nanometer diameters, controlled resistive linking of nearest neighbor dots with conjugated organic molecules and organic rectifiers
  • Keywords
    Boolean functions; combinational circuits; delays; logic arrays; nanotechnology; resonant tunnelling diodes; sequential circuits; Boolean logic; RTDs; charge interactions; chemical self-assembly techniques; close-packed metallic dots; controlled resistive linking; current-voltage characteristics; directionality; double-barrier resonant tunneling diode; fault tolerance; interdot connections; logic circuits; logic functionality; logic gates; nanoelectronic architecture; nanometer diameters; power dissipation; primitive computational cell; rectifying connections; static power dissipation; switching delay; uniform arrays; Boolean functions; Computer architecture; Control system synthesis; Delay estimation; Logic circuits; Nearest neighbor searches; Power dissipation; Resonant tunneling devices; Self-assembly; Sequential circuits;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/5.573742
  • Filename
    573742