DocumentCode :
1478096
Title :
Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2 , \\times , 2 802.11n MIMO WLAN SoC
Author :
Afsahi, Ali ; Behzad, Arya ; Magoon, Vikram ; Larson, Lawrence E.
Author_Institution :
Broadcom Corp., San Diego, CA, USA
Volume :
45
Issue :
5
fYear :
2010
fDate :
5/1/2010 12:00:00 AM
Firstpage :
955
Lastpage :
966
Abstract :
Fully integrated dual-band power amplifiers with on-chip baluns for 802.11n MIMO WLAN applications are presented. With a 3.3 V supply, the PAs produce a saturated output power of 28.3 dBm and 26.7 dBm with peak drain efficiency of 35.3% and 25.3% for the 2.4 GHz and 5 GHz bands, respectively. By utilizing multiple fully self-contained linearization algorithms, an EVM of -25 dB is achieved at 22.4 dBm for the 2.4 GHz band and 20.5 dBm for the 5 GHz band while transmitting 54 Mbs OFDM. The chip is fabricated in standard 65 nm CMOS and the PAs occupy 0.31 mm2 (2.4 GHz) and 0.27 mm2 (5 GHz) area. To examine the reliability of the PAs, accelerated aging tests are performed for several hundreds parts without a single failure.
Keywords :
CMOS integrated circuits; MIMO communication; baluns; life testing; power amplifiers; system-on-chip; wireless LAN; CMOS; MIMO WLAN SoC; accelerated aging tests; bandwidth 2.4 GHz; bandwidth 5 GHz; efficiency 25.3 percent; efficiency 35.3 percent; integrated baluns; linearized dual-band power amplifiers; size 65 nm; voltage 3.3 V; Accelerated aging; Dual band; Impedance matching; MIMO; OFDM; Performance evaluation; Power amplifiers; Power generation; Testing; Wireless LAN; 802.11n; CMOS; MIMO; OFDM; Power amplifier; WLAN; linearization; reliability;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2010.2041401
Filename :
5453310
Link To Document :
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