Digital arithmetic units for a high data rate

The input rate of a digital data processor is determined by the clock speed of the logic used and this is limited by the settling time. The settling time for some key functions can be significantly reduced by modifying the timing of a logic-in-memory system. The clock speed of a multiplier or accumulator can be increased to almost the maximum toggle-speed of the shift register elements used, by conversion from parallel to diagonal timing. A multiplier has been designed which can accept one complete set of input coefficients per clock cycle at these speeds.