Title :
Novel high-speed flip-flop circuit with low power consumption using GaAs junction FETs
Author :
Takano, Chisa ; Wada, Masaki ; Kasahara, J.
Author_Institution :
Sony Corp. Res. Centre, Yokohama, Japan
fDate :
4/25/1991 12:00:00 AM
Abstract :
A novel flip-flop circuit configuration is proposed for very high speed GaAs LSIs. A T-connected flip-flop circuit was fabricated using 0.5 mu m GaAs junction FETs. It operates at a maximum toggle frequency of 7.0 GHz with a power consumption of 10.8 mW.
Keywords :
III-V semiconductors; field effect integrated circuits; flip-flops; gallium arsenide; integrated logic circuits; junction gate field effect transistors; large scale integration; 0.5 micron; 10.8 mW; 7 GHz; GaAs; T-connected; flip-flop circuit; high-speed LSI; junction FETs; logic IC; low power consumption; maximum toggle frequency;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19910475
