Title :
1 V input sampling circuit with improved linearity
Author :
Chang, D. ; Moon, U.
Author_Institution :
Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
fDate :
4/12/2001 12:00:00 AM
Abstract :
A highly linear low-voltage sampling circuit is proposed. Operation under 1 V power supply is possible without compromising linearity. Performance limiting nonlinear MOS switch resistance characteristics are suppressed by a combination of three novel design techniques
Keywords :
CMOS analogue integrated circuits; network synthesis; signal sampling; switched networks; 1 V; LV sampling circuit; design techniques; highly linear sampling circuit; linearity; low-voltage operation; nonlinear MOS switch resistance characteristics; nonlinear characteristics suppression;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010333
