DocumentCode
1479299
Title
Reduced-complexity design for triple-tunable frequency synthesiser
Author
Ryu, Heung-Gyoon ; Kim, Yun-Young ; Yu, Hyeong-Man
Author_Institution
Dept. of Electron. Eng., Chung-Buk Nat. Univ., Cheongju, South Korea
Volume
37
Issue
8
fYear
2001
fDate
4/12/2001 12:00:00 AM
Firstpage
482
Lastpage
484
Abstract
A new design method for a triple-tunable type DDFS-driven PLL frequency synthesiser is presented. Since only a phase accumulator is used in the DDFS (direct digital frequency synthesiser), the other parts of the DDFS such as ROM and a D/A converter can be excluded using the proposed method. Therefore, performance improvements are achieved such as circuit simplicity, reduced power consumption and switching time. In addition, the output of the designed DDFS is processed to provide a jitter-free input reference to the PLL. Simulation results show the validity and performance improvements of the proposed system, compared with the conventional system
Keywords
circuit tuning; direct digital synthesis; phase locked loops; DDFS-driven PLL frequency synthesiser; design method; direct digital frequency synthesiser; jitter-free input reference; performance improvements; phase accumulator; power consumption reduction; reduced-complexity design; switching time reduction; triple-tunable frequency synthesiser;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010323
Filename
919972
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