Reduced-complexity design for triple-tunable frequency synthesiser

A new design method for a triple-tunable type DDFS-driven PLL frequency synthesiser is presented. Since only a phase accumulator is used in the DDFS (direct digital frequency synthesiser), the other parts of the DDFS such as ROM and a D/A converter can be excluded using the proposed method. Therefore, performance improvements are achieved such as circuit simplicity, reduced power consumption and switching time. In addition, the output of the designed DDFS is processed to provide a jitter-free input reference to the PLL. Simulation results show the validity and performance improvements of the proposed system, compared with the conventional system