Power-efficient power-management logic

Since the power consumption has become the key aspect in almost every digital-system design, many advanced power-reduction techniques have been developed to minimize power. The most popular strategy to apply these techniques is adoption of so-called power management. The control signals for the power-management elements are generated by power-management logic. When centralized in one system block, it is referred to as power-management unit (PMU). PMU should also be targeted by power-efficient design techniques. This paper shows the value of power-management inside the PMU, reducing the overall system power consumption. We show that the power-state machines in the PMU can be designed in such a way that only necessary components stay active in the sleep mode. Experimental results illustrate that approximately 30% of power-state machines power can be saved.