Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature

In this paper, the minimum operating voltage of master-slave flip-flops made in advanced fully-depleted silicon on insulator (FDSOI) technology, is studied through silicon measurements. A shift register of 1024 master-slave flip-flops has been fabricated in 28nm FDSOI technology in order to study the minimum operating voltage with respect to a wide back bias range allowed by the FDSOI technology. We show that a maximum yield is obtained for an optimum back bias couple (VBP for PMOS, VBN for NMOS) resulting from a tradeoff between speed and currents ratios. Results are given for a chain of 1, 16, 128, and 1024 FFs in series as well as for two different temperatures (30°C and 80°C). The minimum operating voltage of 1024 FFs is 230mV at 30°C for a back biasing of (VBP,VBN) = (-0.5V,0.5V) and 299mV at 80°C with (VBP,VBN) = (0V,0V).