Write scheme for multiple Complementary Resistive Switch (CRS) cells

Amongst emerging technologies with the potential to usher in a new generation of Non Volatile Memory (NVM) is the memristor. The memristor makes it possible to build simple and highly dense memory structure via cross point architecture. Memristor array however suffers exponentially from sneak path leakages as array size increases, which leads to excessive power consumption and poor data integrity. Complementary Resistive Switch (CRS) was proposed to mitigate the sneak-path problem. However, when writing into multiple cells in CRS-based memory array, the state of unselected and and half-selected cell(s) in the array are affected in an undesired way depending on the polarity, magnitude and duration of the voltage applied during the write operation. The effect of these disturbance to non-selected cell(s) is a resultant corrupted output in subsequent read operation on these cell(s). In this paper, we reviewed the basic operation of the memristor and CRS cell in relation to their application as a memory device. Finally, we implemented an improved scheme for writing alternating data patterns into multiple cells in CRS-based memory array, we also examine how the initial state of the cell affects the performance of this scheme.