A computer algorithm for state table reduction

As part of a large research programme on the use of computer aids for logic circuit design, it was required to provide an algorithm for the reduction of sequential circuit state tables (completely or incompletely specified). This paper discusses the theoretical problems of state reduction and demonstrates how a rapid solution may be obtained based on the determination and use of a closure function associated with each maximal or prime compatible set. The use of several heuristics ensures that a near-minimal solution to the subsequent closed-cover problem is always obtained, rather than the absolute minimum that is theoretically possible but computationally impracticable. This is in keeping with the overall design philosophy of producing a viable engineering design rather than the theoretical optimum usually dictated by switching theory. The algorithm has been programmed and the paper further discusses the data structures used and problems encountered in its implementation.