DocumentCode :
147980
Title :
VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms
Author :
Kumar Rethinagiri, Santhosh ; Palomar, Oscar ; Arias Moreno, Javier ; Unsal, Ozan ; Cristal, Adrian
Author_Institution :
Barcelona Supercomput. Center, Barcelona, Spain
fYear :
2014
fDate :
Sept. 29 2014-Oct. 1 2014
Firstpage :
1
Lastpage :
8
Abstract :
Using low-power symmetric multi-cores on FPGAs are becoming ubiquitous in embedded computing. This is due to the emergence of power and energy as key design metrics, as important as performance. This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow. In this paper, we propose a simulation based virtual platform power and energy estimation tool for heterogeneous Multiprocessor System-on-Chip (MPSoC) based platforms. There are two steps involved in this tool development. The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for different parts of the system. This is a one-time activity. In the second step, a simulation based virtual platform framework is developed to accurately grab the activities used in the related power models generated in the first step. The combination of the two steps leads to a hybrid power estimation, which gives a better trade-off between accuracy and speed. The proposed tool is automated and also scalable for exploring complex embedded multi-core architectures. The efficiency of the proposed tool is validated through multi-cores/processors designed around the FPGAs and extended to accommodate futuristic multi-processors/cores for a reliable energy based DSE. The obtained power/energy estimation results provide less than 4% of error for single core processor, 8% for dual-core processor and 9% for heterogeneous MPSoC based systems when compared to real board measurements.
Keywords :
field programmable gate arrays; system-on-chip; FPGA platforms; VPPET; embedded computing; heterogeneous MPSoC; heterogeneous multiprocessor system-on-chip; low-power symmetric multicores; virtual platform power and energy estimation tool; Algorithm design and analysis; Field programmable gate arrays; Hardware; Program processors; Surface treatment; Transform coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International Workshop on
Conference_Location :
Palma de Mallorca
Type :
conf
DOI :
10.1109/PATMOS.2014.6951910
Filename :
6951910
Link To Document :
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