Rapid yield estimation as a computer aid for analog circuit design

Author

Mukherjee, Tamal ; Carley, Richard L.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

26

Issue

3

fYear

1991

fDate

3/1/1991 12:00:00 AM

Firstpage

291

Lastpage

299

Abstract

A rapid yield estimation methodology that aids the analog circuit designer in making design tradeoffs that improve yield is presented. This methodology is based on using hierarchical evaluation of analysis equations, rather than simulations, to predict circuit performance. The new analog rapid yield estimation (ARYE) method has been used to predict the yield of two-stage operational amplifiers and has been incorporated into the Carnegie Mellon University (CMU) analog design system (ACACIA). An example of how ARYE allows analog designers to quickly explore the impact of design changes on yield is presented. The primary goal of ARYE is to make numerous early predictions of parametric yield economical for the analog circuit designer

Keywords

analogue circuits; circuit CAD; operational amplifiers; ACACIA; ARYE; Carnegie Mellon University; analog circuit design; circuit performance; design tradeoffs; hierarchical evaluation; parametric yield; two-stage operational amplifiers; yield estimation methodology; Analog circuits; Analog computers; Analytical models; Circuit optimization; Circuit simulation; Computational modeling; Equations; Performance analysis; Predictive models; Yield estimation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75008

Filename

75008