Design of digital filters for advanced telecommunications ASIC´s using a special-purpose silicon compiler

Complex DSP (digital signal processor) ASICs (application-specific integrated circuits) typically feature high-quality filters implemented as dedicated blocks. FIDYS (filter 1di synthesis system) is a new VLSI recursive filter compiler, specifically designed to meet those needs. It is fully integrated from behavioral frequency template specifications down to layout. It comprises a specific approximation and synthesis procedure, the generation of a systolic architecture with parameterized pipelining based on dedicated bit-serial operators, and final generation of a densely packed layout based on a minimal dedicated set of 1-μm CMOS basic cells. A lossless discrete integrator ladder filter structure is used. It features an outstanding low sensitivity and a high degree of modularity and regularity that directly result in streamlined hardware and an efficient placement with minimal routing overhead. Examples of representative applications for telecommunications circuits are presented