High-density central I/O circuits for CMOS

An I/O circuit design for VLSI CMOS is described that reduced the percentage of chip area occupied by I/O circuits from roughly 22% to under 3% for a 256 I/O chip. The technique, implemented in the IBM RISC System/6000 workstation processor chips, uses stackable macros to improve density per I/O signal by 10 times. The reorganization of the I/O structure relies on a top layer of metal dedicated to I/O circuit-to-pad wiring and power distribution. It takes full advantage of C4 solder bond package connection technology, which allows package connections to be located over chip circuitry. Decoupling I/O circuit layout from package connection layout and grouping by identical circuit type permits the full range of layout optimization techniques to be applied. I/O circuits are produced that are fully compatible with internal circuit terrain