A digital interpolation filter chip with 32 programmable coefficients for 80 MHz sampling frequency

A digital interpolation filter chip with 32 programmable coefficients designed for baseband pulse shaping in digital microwave radio modems is presented. The chip was designed for a maximum sampling frequency of 80 MHz, under worst-case conditions. The desired throughput rate is achieved by applying a pipelined carry-save arithmetic. Although an optimized pipeline scheme was used, the chip complexity leads to a high capacitive clock load. The synchronization problems and the switching noise problems resulting from this high clock load were solved by dividing the clock system into subsystems and introducing and intended clock skew between the subsystems and by applying a power supply concept in which the global supply lines are consistently routed in a sandwich structure to create an on-chip buffer capacitance. The chip contains 160000 transistors on a silicon area of 78 mm². Typical samples were tested, and although they were fabricated in a moderate 1.5-μm CMOS technology, their full logical functionality was verified for sampling frequencies of up to 220 MHz