DocumentCode :
1481637
Title :
SYMCELL-a symbolic standard cell system
Author :
Ramachandran, K. ; Cordell, R.R. ; Daly, D.F. ; Deutsch, D.N. ; Kwan, A.F.
Author_Institution :
Bellcore, Red Bank, NJ, USA
Volume :
26
Issue :
3
fYear :
1991
fDate :
3/1/1991 12:00:00 AM
Firstpage :
449
Lastpage :
452
Abstract :
A SYMCELL system is used to create research VLSI prototypes because it permits rapid realization of reasonably high-performance chips. The SYMCELL process flow consists of library creation; schematic capture and logic simulation; netlist translation; layout planning (cell placement and global routing); layout implementation (cell gridding and fine routing); layout verification and simulation; and chip assembly. SYMCELL is a standard cell system that enables cells to be created, placed, and globally routed symbolically. After this symbolic realization, cell rows are compacted and pitch-matched and channels are routed for a specific set of layout rules. The symbolic cell libraries can be maintained independently of the process layout rules, and new cells can be created with the ease of symbolic layout. The system is especially useful in research because of the ease with which the cell library can be mapped to new sets of layout rules
Keywords :
VLSI; application specific integrated circuits; circuit layout CAD; integrated circuit technology; ASIC design; cell gridding; cell placement; channel routeing; chip assembly; custom design; fine routing; global routing; high-performance chips; layout planning; layout verification; library creation; logic simulation; netlist translation; research VLSI prototypes; schematic capture; simulation; symbolic standard cell system; Capacitance; Compaction; Counting circuits; Geometry; Libraries; Mesh generation; Pattern matching; Productivity; Prototypes; Very large scale integration;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.75035
Filename :
75035
Link To Document :
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