DocumentCode
1481826
Title
A 4 Mb NAND EEPROM with tight programmed V t distribution
Author
Momodomi, Masaki ; Tanaka, Tomoharu ; Iwata, Yoshihisa ; Tanaka, Yoshiyuki ; Oodaira, Hideko ; Itoh, Yasuo ; Shirota, Riichiro ; Ohuchi, Kazunori ; Masuoka, Fujio
Author_Institution
Toshiba Corp., Kawasaki, Japan
Volume
26
Issue
4
fYear
1991
fDate
4/1/1991 12:00:00 AM
Firstpage
492
Lastpage
496
Abstract
Described is a 5-V-only 4-Mb (512K×8 b) NAND EEPROM (electrically erasable programmable ROM) with tight programmed threshold voltage (V t) distribution, controlled by a novel program-verify technique. A tight programmed V t distribution width of 0.8 V for the 4 Mb cell array is achieved. By introducing a compact row-decoder circuit, a die size of 7.28 mm×15.31 mm is achieved using 1.0 μm design rules. A unique twin p-well structure has made it possible to realize low-power 5 V-only erase/program operation easily and to achieve 100 K-cycle endurance
Keywords
CMOS integrated circuits; EPROM; NAND circuits; VLSI; integrated memory circuits; 1 micron; 4 Mbit; 5 V; NAND EEPROM; electrically erasable programmable ROM; low-power 5 V-only erase/program operation; memory IC; n-well CMOS; program-verify technique; programmed threshold voltage distribution; row-decoder circuit; twin p-well structure; EPROM; Energy consumption; Equivalent circuits; Flash memory; Magnetics; Manufacturing processes; Nonvolatile memory; Portable computers; Threshold voltage; Voltage control;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.75044
Filename
75044
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