A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

Author

Ohba, Atsushi ; Ohbayashi, Shigeki ; Shiomi, Toru ; Takano, Satoshi ; Anami, Kenji ; Honda, Hiroki ; Ishigaki, Yoshiyuki ; Hatanaka, Masahiro ; Nagao, Shigeo ; Kayano, Shimpei

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

26

Issue

4

fYear

1991

fDate

4/1/1991 12:00:00 AM

Firstpage

507

Lastpage

512

Abstract

A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 μm BiCMOS process. An improved buffer with a high-level output of nearly V_CC is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a sense-amplifier switch circuit with no access degradation. A wired-OR demultiplexer for the ×1 output, having the same critical path as the ×4 output circuit, allows for the same access time between the two modes. The ×1 or ×4 mode is electrically selected by the external signal. A simplified programming redundancy technology, shift redundancy, is utilized. Address programming is performed by cutting only one fuse in the shift redundancy. The RAM operates at the ECL-10K level with an access time of 7 ns. and the power dissipation at 50 MHz is 600 mW for the × mode

Keywords

BIMOS integrated circuits; SRAM chips; VLSI; emitter-coupled logic; redundancy; 0.8 micron; 1 Mbit; 50 MHz; 600 mW; 7 ns; BiCMOS; ECL SRAM; access time; configurable bit organization; emitter coupled logic; level converter circuit; power dissipation; programming redundancy technology; sense-amplifier switch circuit; shift redundancy; static RAM; wired-OR demultiplexer; BiCMOS integrated circuits; Coupling circuits; Degradation; Fuses; Logic; MOSFETs; Power dissipation; Random access memory; Switches; Switching circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.75047

Filename

75047