Title :
Fast-access BiCMOS SRAM architecture with a VSS generator
Author :
Douseki, Takakuni ; Ohmori, Yasuo ; Yoshino, Hideo ; Yamada, Junzo
Author_Institution :
NTT LSI Lab., Kanagawa, Japan
fDate :
4/1/1991 12:00:00 AM
Abstract :
A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with VSS generator has been developed. Two key circuits, a VSS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described
Keywords :
BIMOS integrated circuits; SRAM chips; VLSI; emitter-coupled logic; 0.8 micron; 256 kbit; 5 ns; BiCMOS SRAM architecture; CMOS memory cells; ECL interface SRAM; VSS generator; address access time; all-bipolar peripheral circuits; current switch level converter; emitter coupled logic; external supply voltage; high-speed operation; internal MOS level; scaled-down devices; static RAM; BiCMOS integrated circuits; CMOS logic circuits; CMOS memory circuits; Coupling circuits; Logic devices; MOSFETs; Random access memory; Read-write memory; Switches; Switching circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
