A web based tool for teaching hardware design based on the plain simple hardware description language

In this paper, a new online learning tool is presented. The goal is to improve the learning experience for designing hardware on register transfer level (RTL)-level by facilitating collaboration and allowing a more agile development cycle. It also enables the inspection of the learning process of the students. When students have to learn RTL hardware-design, usually either Verilog or VHDL are used as hardware description language. Those languages do not just have an unfamiliar syntax and programming paradigm for the students (they are not sequential, but rather describe the wiring of components), they also come with complex tools. During the hands-on part of the lecture, a lot of time is spent in learning the functions (and bugs) of each tool involved. It also happens that VHDL was originally designed for a different purpose and thus accepts input that is not necessarily fit for synthesis for FPGAs, which are primarily used as target for those hardware designs. Much to the frustration of the students, it is also rather easy to create a mismatch between what the simulation does and how the design behaves on the actual hardware. This does not only result in a highly unsatisfying learning experience, as ”learning” is mostly about understanding the tools and their output, but it also distracts from the real goal of learning how to properly design hardware. A novel programming language called PSHDL, the ”plain simple hardware description language”, keeps the parallelism paradigm of VHDL and Verilog, but provides a significantly improved workflow. This workflow and its features are outlined in this paper. The improvements are not just for the student side, but also allow the teacher to take a direct look at the students´ progress and learning path. This information could then be used to improve the whole learning experience.