Stability of hydrogenated polymorphous silicon thin-film transistors under DC electrical stress

The authors fabricated bottom-gate (BG) back-channel etched (BCE) thin-film transistors with hydrogenated polymorphous silicon (pm-Si:H) as the channel material. This material is obtained using the same low-cost plasma-enhanced chemical vapour deposition (PECVD) techniques as amorphous silicon. The authors first show the improvement of the threshold voltage stability of pm-Si:H TFTs under bias stress compared to a-Si:H counterparts. Then, pm-Si:H TFTs degradation is investigated under different gate bias stress conditions. It has been found that the degradation mechanisms are dependent on the gate stress conditions involving state creation in the channel material and charge trapping at the channel/gate SiN_x interface.