A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS

Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3-μm CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, and occupies 40 kmil² (26 mm²), with a single 5-V supply and two-phase nonoverlapping clock