Title :
A high-speed low-power JFET pull-down ECL circuit
Author :
Shin, Hyun J. ; Lu, Pong-F ; Chuang, Ching-T
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
4/1/1991 12:00:00 AM
Abstract :
An active pull-down output stage that utilizes a composite junction FET (JFET), applied in a high-speed low-power emitter-coupled logic (ECL) circuit, is described. The composite JFET structure is produced by modifying the existing bipolar transistor layout so that a p-channel JFET is formed next to an n-p-n transistor without need of any extra process steps. This p-channel JFET is a four-terminal device: the intrinsic base region defines the channel, the two separate extrinsic bases become the source and drain, the emitter region is the primary gate, and the collector is used as the back gate. The JFET has the same doping profile as the n-p-n bipolar transistor in the intrinsic device region. Simulation results based on a 0.8-μm double poly-Si, self-aligned bipolar technology indicate that the circuit with a typical loading at a power consumption of 1 mW per gate offers a 24% improvement in the pull-down delay and a 53% improvement in the load driving capability compared with the conventional ECL circuit
Keywords :
bipolar integrated circuits; emitter-coupled logic; integrated logic circuits; junction gate field effect transistors; 0.8 micron; 1 mW; active pull-down output stage; composite junction FET; double poly-Si; emitter-coupled logic; four-terminal device; load driving capability; low-power JFET; monolithic IC; n-p-n transistor; p-channel; polycrystalline Si; polysilicon; power consumption; pull-down ECL circuit; pull-down delay; self-aligned bipolar technology; BiCMOS integrated circuits; Circuit simulation; Degradation; Delay; Energy consumption; JFET circuits; MOS devices; MOSFETs; Parasitic capacitance; Solid state circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
