Design of DDFS-driven PLL frequency synthesizer with reduced complexity

Author

Ryu, Heung-Gyoon ; Kim, Yun-Young ; Yu, Hyeong-Man ; Ryu, Sang-Burm

Author_Institution

Dept. of Electron. Eng., Chung-Buk Nat. Univ., Cheongju, South Korea

Volume

47

Issue

1

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

194

Lastpage

198

Abstract

DDFS-driven PLL synthesizer has a high frequency resolution and wide frequency bandwidth. Since the output of DDFS is a synthesized analog signal, a waveform shaper is needed to provide the digital input for a DDFS-driven PLL synthesizer using the digital type phase detector. Furthermore, a lot of components in a DDFS unit can increase the switching time and the power consumption. In this paper, we propose a new design method of a DDFS-driven PLL synthesizer, which does not need the waveform shaper as well as the extra circuits of DDFS. As a result, the proposed method makes improvements to such quality factors as switching time and power consumption, compared with the conventional DDFS-driven PLL frequency synthesizer

Keywords

Q-factor; circuit complexity; digital phase locked loops; direct digital synthesis; DDFS-driven PLL frequency synthesizer; complexity; frequency bandwidth; frequency resolution; power consumption; quality factors; switching time; Bandwidth; Circuits; Design methodology; Detectors; Energy consumption; Frequency synthesizers; Phase detection; Phase locked loops; Signal resolution; Signal synthesis;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.920440

Filename

920440