• DocumentCode
    1482716
  • Title

    High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm

  • Author

    Chen, Xiaoheng ; Wang, Chung-Li

  • Author_Institution
    SanDisk Corp., Milpitas, CA, USA
  • Volume
    59
  • Issue
    11
  • fYear
    2012
  • Firstpage
    2784
  • Lastpage
    2794
  • Abstract
    Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. The excessive computational complexity and memory usage of the existing decoder designs are considerably expensive for practical applications. Based on a newly proposed simplified min-sum algorithm, which only has 0.05-0.1 dB performance loss against the sum-product algorithm, a highly efficient decoder architecture is developed. Compared with the existing works, our design has three advantages. First, the design increases the parallelism and throughput of the decoder by three to four times. The implementation results for the decoder show high throughput of 64 Mbps at 15 iterations. Second, this design saves memory usage by 38% to 76%. Third, this design shows 2.64 × area efficiency improvement even compared with the most state-of-the-art design.
  • Keywords
    channel coding; computational complexity; decoding; parity check codes; bit rate 64 Mbit/s; channel impairments; excessive computational complexity; high-throughput efficient nonbinary LDPC decoder design; loss 0.05 dB to 0.1 dB; nonbinary low-density parity-check code; simplified min-sum algorithm; sum-product algorithm; Algorithm design and analysis; Bit error rate; Complexity theory; Computer architecture; Decoding; Parity check codes; Throughput; Decoder architecture; VLSI design; error control coding; low-density parity-check (LDPC) codes; non-binary;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems I: Regular Papers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-8328
  • Type

    jour

  • DOI
    10.1109/TCSI.2012.2190668
  • Filename
    6177696