Targeting Design, Verification, and Test Challenges

This general-interest issue of D&Tfeatures articles on recent advances in design methods such as customization to achieve higher efficiency in terms of power and performance, accurate power estimation for multiprocessor system-on-chips (MPSoCs) based on network-on-chips (NoCs), and low-power and reliable on-chip interconnects. This issue also includes articles on testbench acceleration, testing for small-delay defects to reduce test escapes, and synthesis of scan trees to minimize test time.