Low-Power, Resilient Interconnection with Orthogonal Latin Squares

Author

Lee, Seung Eun ; Yang, Yoon Seok ; Choi, Gwan S. ; Wu, Wei ; Iyer, Ravi

Author_Institution

Seoul Nat. Univ. of Sci. & Technol., Seoul, South Korea

Volume

28

Issue

2

fYear

2011

Firstpage

30

Lastpage

39

Abstract

A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55% energy reduction, with only a small area overhead and no loss in reliability.

Keywords

error correction codes; multiprocessor interconnection networks; system-on-chip; CMOS technology; energy consumption; energy-efficient on-chip interconnection network; error-correcting code; low- swing signaling; orthogonal latin squares code; reliability; transient errors; Crosstalk; Decoding; Encoding; Error correction codes; IP networks; OFDM; System-on-a-chip; ECC; OLSC; design and test; error-correcting code; on-chip interconnection; orthogonal Latin square; resilience and low power design;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/MDT.2011.35

Filename

5739839