DocumentCode :
1482851
Title :
Hybrid Testbench Acceleration for Reducing Communication Overhead
Author :
Chuang, Chin-Lung ; Liu, Chien-Nan
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jungli, Taiwan
Volume :
28
Issue :
2
fYear :
2011
Firstpage :
40
Lastpage :
51
Abstract :
Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator and with only 0.57% hardware overhead.
Keywords :
benchmark testing; logic design; performance evaluation; chip prototypes; communication overhead; hardware accelerators; hardware overhead; hybrid embedded testbench acceleration; Acceleration; Central Processing Unit; Detectors; Emulation; Hardware design languages; Power transmission lines; Testing; HETA; design and test; functional verification; hardware-accelerated simulation; testbench acceleration;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2011.33
Filename :
5739840
Link To Document :
بازگشت