A Metric to Target Small-Delay Defects in Industrial Circuits

Author

Yilmaz, Mahmut ; Chakrabarty, Krishnendu ; Tehranipoor, Mohammad

Author_Institution

Adv. Micro Devices, Sunnyvale, CA, USA

Volume

28

Issue

2

fYear

2011

Firstpage

52

Lastpage

61

Abstract

Timing-related defects are a major cause of test escapes and field returns for very deep-submicron (VDSM) integrated circuits. Small-delay variations induced by crosstalk, process variations, power supply noise, and resistive opens and shorts can cause timing failures in a design, leading to quality and reliability concerns. This article describes the authors´ work with a previously proposed test-grading technique that uses output deviations for screening small-delay defects.

Keywords

integrated circuit design; integrated circuit reliability; integrated circuit testing; crosstalk; industrial circuits; output deviations; power supply noise; process variations; resistive opens; resistive shorts; small-delay defects; test-grading technique; timing failures; timing-related defects; very deep-submicron integrated circuits; Automatic test pattern generation; Circuit faults; Delay; Logic gates; Runtime; ATPG; DFT; defects; delay test; design and test; output deviations; screening; small-delay defects; very deep-submicron;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/MDT.2011.26

Filename

5739841