DocumentCode :
1483087
Title :
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000
Author :
Sarawadekar, Kishor ; Banerjee, Swapna
Author_Institution :
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India
Volume :
21
Issue :
6
fYear :
2011
fDate :
6/1/2011 12:00:00 AM
Firstpage :
825
Lastpage :
836
Abstract :
The embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression system. Various applications, such as medical imaging, satellite imagery, digital cinema, and others, require high speed, high performance EBCOT architecture. Though efficient EBCOT architectures have been proposed, hardware requirement of these existing architectures is very high and throughput is low. To solve this problem, we investigated rate of concurrent context generation. Our paper revealed that in an image rate of four or more context pairs generation is about 68.9%. Therefore, to encode all samples in a stripe-column, concurrently a new technique named as compact context coding is devised. As a consequence, high throughput is attained and hardware requirement is also cut down. The performance of the matrix quantizer coder is improved by operating renormalization and byte out stages concurrently. The entire design of EBCOT encoder is tested on the field programmable gate array platform. The implementation results show that throughput of the proposed architecture is 163.59 MSamples/s which is equivalent to encoding 1920p (1920 × 1080, 4:2:2) high-definition TV picture sequence at 39 f/s. However, only bit plane coder (BPC) architecture operates at 315.06 MHz which implies that it is 2.86 times faster than the fastest BPC design available so far. Moreover, it is capable of encoding digital cinema size (2048 × 1080) at 42 f/s. Thus, it satisfies the requirement of applications like cartography, medical imaging, satellite imagery, and others, which demand high-speed real-time image compression system.
Keywords :
block codes; field programmable gate arrays; high definition television; image coding; image sequences; parallel architectures; quantisation (signal); BPC architecture; EBCOT encoder; JPEG 2000; bit plane coder architecture; compact context coding; digital cinema; embedded block coding with optimized truncation; field programmable gate array; frequency 315.06 MHz; high performance EBCOT architecture; high-definition TV picture sequence; high-speed real-time image compression system; image compression; matrix quantizer coder; pass-parallel architecture; Computer architecture; Context; Discrete wavelet transforms; Encoding; Image coding; Throughput; Transform coding; Embedded block coding with optimized truncation (EBCOT); JPEG 2000; MQ coder; VLSI architecture; field programmable gate array (FPGA);
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/TCSVT.2011.2133450
Filename :
5740317
Link To Document :
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