• DocumentCode
    1483142
  • Title

    An interconnect-centric design flow for nanometer technologies

  • Author

    Cong, Jason

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
  • Volume
    89
  • Issue
    4
  • fYear
    2001
  • fDate
    4/1/2001 12:00:00 AM
  • Firstpage
    505
  • Lastpage
    528
  • Abstract
    As the integrated circuits (ICs) are scaled into nanometer dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. This paper presents the ongoing research effort at UCLA in developing an interconnect-centric design flow, including interconnect planning, interconnect synthesis, and interconnect layout, which allows interconnect design and optimization to be properly considered at every level of the design process. Efficient interconnecter performance estimation models and tools at various levels are also developed to support such an interconnect-centric design flow
  • Keywords
    integrated circuit design; integrated circuit interconnections; integrated circuit modelling; nanotechnology; integrated circuit; interconnect design optimization; interconnect layout; interconnect planning; interconnect synthesis; interconnect-centric design flow; nanometer technology; performance estimation model; Capacitance; Delay; Design automation; Design optimization; Frequency; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit noise; Integrated circuit technology; Transistors;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/5.920581
  • Filename
    920581