On-chip wiring design challenges for gigahertz operation

Author

Deutsch, Alina ; Coteus, Paul W. ; Kopcsay, Gerard V. ; Smith, Howard H. ; Surovic, Christopher W. ; Krauter, Byron L. ; Edelstein, Daniel C. ; Restle, Phillip J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

89

Issue

4

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

529

Lastpage

555

Abstract

This paper reviews the status of present day on-chip wiring design methodologies and understanding. A brief explanation is given of the fundamental transmission-line properties that should be considered for accurate prediction of crosstalk, common-mode noise and clock skew. The deficiencies of RC-circuit representation are highlighted and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections. Such techniques are believed to teach designers how to make better use of available technologies and help them architect systems that operate with many-GHz clock rates

Keywords

crosstalk; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; transmission lines; RC circuit model; clock skew; common-mode noise; crosstalk; gigahertz operation; integrated circuit design; on-chip wiring; transmission line; Capacitance; Clocks; Coupling circuits; Crosstalk; Delay effects; Design methodology; Hip; Propagation delay; Transmission lines; Wiring;

fLanguage

English

Journal_Title

Proceedings of the IEEE

Publisher

ieee

ISSN

0018-9219

Type

jour

DOI

10.1109/5.920582

Filename

920582