Title :
Architectural yield optimization for WSI
Author :
Harden, Jim C. ; Stader, N.R.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fDate :
1/1/1988 12:00:00 AM
Abstract :
A novel methodology for investigating wafer-scale integration (WSI) designs is proposed. This methodology combines the results of work on integrated circuit yield modeling with a study of the effects of system architecture in large-area integrated circuit yield. This work provides a hierarchical framework in which computing structures may be analyzed to determine functionality on a wafer scale and develops methods by which this functionality can be optimized
Keywords :
VLSI; circuit reliability; computer architecture; failure analysis; fault tolerant computing; redundancy; architectural yield optimisation; computing structures; integrated circuit yield modeling; wafer-scale integration; Binary trees; Circuit faults; Integrated circuit modeling; Integrated circuit packaging; Integrated circuit yield; Optimization methods; Redundancy; Semiconductor device modeling; Semiconductor device packaging; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
