Throughput analysis of cache-based multiprocessors with multiple buses

Author

Dubois, Michel

Author_Institution

Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA

Volume

37

Issue

1

fYear

1988

fDate

1/1/1988 12:00:00 AM

Firstpage

58

Lastpage

70

Abstract

The performance of cache-based multiprocessors for general-purpose computing and for multitasking is analyzed with simple throughput models. A private cache is associated with each processor, and multiple buses connect the processors to the shared, interleaved memory. Simple models based on dynamic instruction mix statistics are introduced to evaluate upper bounds on the throughput when independent tasks are run on each processor. With these models, one can obtain a first estimate of the MIPS (millions of instructions per second) rate of a multiprocessor

Keywords

buffer storage; multiprocessing systems; performance evaluation; cache-based multiprocessors; dynamic instruction mix statistics; general-purpose computing; multiple buses; multitasking; performance; private cache; shared interleaved memory; throughput; Analytical models; Data structures; Iterative algorithms; Multitasking; Partial differential equations; Partitioning algorithms; Performance analysis; Statistics; Throughput; Upper bound;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.75139

Filename

75139