Optimized layout of MOS cells

Author

Thuau, Ghislaine ; Saucier, Gabriále

Author_Institution

Lab. Circuits et Syst., Inst. Nat. Polytech. de Grenoble, France

Volume

37

Issue

1

fYear

1988

fDate

1/1/1988 12:00:00 AM

Firstpage

79

Lastpage

87

Abstract

A design method using both logical optimization and optimized topological arrangements is described. Starting from a minimized Boolean function, a synthesis of an optimized well-structured network is obtained. The most original aspect of this approach is a transistor merging procedure leading to a nonseries-parallel network while maintaining a systematic layout. An extension to the synthesis of several functions relies on transistor mergings between functions and allows comparisons with a PLA implementation. Gains in both area and performance are obtained

Keywords

circuit layout CAD; field effect integrated circuits; logic design; minimisation of switching nets; logical optimization; minimized Boolean function; nonseries-parallel network; optimised MOS cell layout; optimized topological arrangements; transistor merging procedure; well-structured network; Boolean functions; Design methodology; Design optimization; Input variables; Integrated circuit interconnections; Merging; Network synthesis; Programmable logic arrays; Switches; Transfer functions;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.75140

Filename

75140