Title :
Developing a high-level fault simulation standard
Author :
Deniziak, Stanislaw ; Sapiecha, Krzysztof
Author_Institution :
Dept. of Comput. Sci., Kielce Univ. of Technol., Poland
fDate :
5/1/2001 12:00:00 AM
Abstract :
Recent developments in deep-submicron technology challenge current integrated circuit testing methods. The increasing complexity of designed systems makes test development more time-consuming. Moreover, nanometer technology introduces new defects or higher data rate errors. To reduce manufacturing costs and time to market, we must develop efficient fault detection and location methods. Using high-level fault simulation stimulates the development of new, fast test-generation algorithms that take into consideration functional features of the system under test or its components. Moreover, all synthesis tools migrate to higher levels, and we believe that this will improve ATPG tools as well
Keywords :
automatic test pattern generation; fault simulation; high level synthesis; integrated circuit testing; standards; ATPG tools; automatic test pattern generation; data rate errors; deep-submicron technology; defects; fault detection methods; fault location methods; functional features; high-level fault simulation standard; high-level synthesis tools; integrated circuit testing methods; manufacturing costs; nanometre technology; system complexity; test development; test generation algorithms; time to market; Circuit faults; Circuit simulation; Circuit testing; Costs; Integrated circuit technology; Integrated circuit testing; Manufacturing; Standards development; System testing; Time to market;
