Electrical isolation design rule for GaAs integrated circuits fabricated on semi-insulating substrates

The characteristics of n-semi-insulating-n (n-si-n) structures that dictate the design rules for electrical isolation between active devices of GaAs integrated circuits fabricated on semi-insulating substrates are studied by one-dimensional and two-dimensional numerical simulations. It is found that the I-V characteristics of these structures are characterized by sharp current-rising regions which result from a potential barrier lowering effect caused by the punchthrough phenomenon. Simplified expressions are derived for quick evaluation of the punchthrough voltages for both one-dimensional and two-dimensional analyses. For a given operating voltage, the one-dimensional calculation gives a larger spacing between n regions in a n-si-n structure for onset of large current flow than does the two-dimensional analysis. Therefore, the spacing obtained from one-dimensional results can be used as a conservative design criterion for device isolation. For more aggressive electrical isolation design, two-dimensional simulation is necessary since it provides more accurate results