Title :
An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing
Author :
Venes, Ardie G W ; van-de-Plassche, R.J.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fDate :
12/1/1996 12:00:00 AM
Abstract :
An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-μm standard digital CMOS technology
Keywords :
CMOS integrated circuits; analogue-digital conversion; interpolation; 0.5 micron; 3.3 V; 44 dB; 75 to 80 MHz; 8 bit; 80 mW; A/D converter; CMOS folding ADC; SNR; analog-to-digital converter; distributed track/hold preprocessing; interpolation; signal-to-noise ratio; Analog-digital conversion; Bandwidth; CMOS technology; Clocks; Data preprocessing; Frequency conversion; Interpolation; Power dissipation; Signal to noise ratio; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of