Wire packing - a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution

By focusing on chip-wide slices of the global routing grid, making a few mild geometric assumptions about layer use, and suitably abstracting pin details, we derive an efficient integer linear programming formulation for track/layer assignment. The key technical insight is to model all constraints both geometric and crosstalk - as cliques in an appropriate conflict graph; these cliques can be extracted quickly from the interval structure of wires in a slice. We develop a “strong” linear relaxation of this problem that almost always yields the integral optimum; this solution gives us directly the maximum number of wires that can be packed legally without crosstalk risk. Experiments on synthetic netlists that match statistics of wire layouts from industrial 0.25-μm designs demonstrate that we can pack 100-1000 wires optimally or, at worst, a very few overflows in seconds